Field of the Invention
The present invention relates generally to test circuits for a memory device and a semiconductor integrated device including the test circuit, and particularly to a test circuit for a flash memory and a semiconductor integrated device that incorporates the flash memory and the test circuit combined therein, such as an ASIC.
Description of the Related Art
As the capacity and speed of an LSI chip increase, a cost required to test the LSI chip increases more and more. A test facilitating technology called BIST (built-in self test), in which part of a tester function of testing an LSI chip is incorporated as a test circuit in the LSI chip, is employed as an attempt to lower the test cost.
For example, Patent Document 1 (Japanese Patent Application Publication No. 2003-077296) discloses a multichip-package (MCP) semiconductor device in which a logic chip and a memory chip are incorporated in a common package. The semiconductor device includes a selector/output circuit that selects either a memory access signal or an access signal for a memory test and executes a logic-chip-to-memory-chip access operation test when the access signal for a memory test is selected.
Patent Document 2 (Japanese Patent Application Publication No. 2008-108326) relates to a storage device that incorporates a nonvolatile memory, such as a NOR flash memory, and a self-test method, and discloses a technology for executing a self-test in a test circuit incorporated in the storage device itself. More specifically, Patent Document 2 discloses a storage device including a single chip that incorporates a nonvolatile memory that stores test step items and parameters, and a control circuit that causes the nonvolatile memory to undergo the test steps using the step items and the parameters.